Automatic layout and optimization of static CMOS cells

A novel algorithm for generating complex CMOS gates from Boolean factored forms is presented. It uses a hierarchical composition of cells corresponding to the subexpressions of a Boolean factored form. Composition rules that allow for constructing the gates in linear time are derived. Cell width/height tradeoffs are made possible to ease pitch-matching. The algorithm has been coded in a pair of programs, called Castor and Pollux. The programs have been used to generate moderately complex layouts, consisting of circuits having up to a few thousand transistors. They can also be used to automatically generate a library of logic gates.<
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