A 46-ns 1-Mbit CMOS SRAM

A 1-Mb (128 K*8-bit) CMOS static RAM (SRAM) with high-resistivity load cell has been developed with 0.8- mu m CMOS process technology. Standby power is 25 mu W, active power 80 mW at 1-MHz WRITE operation, and access time 46 ns. The SRAM uses a PMOS bit-line DC load to reduce power dissipation in the WRITE cycle, and has a four-block access mode to reduce the testing time. A small 4.8*8.5- mu m/sup 2/ cell has been realized by triple-polysilicon layers. The grounded second polysilicon layer increases cell capacitance and suppresses alpha -particle-induced soft errors. The chip size is 7.6*12.4 mm/sup 2/.<
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