A novel dual p/sup -//p/sup +/ poly gate CMOS VLSI technology

A CMOS VLSI technology using p/sup -/ and p/sup +/ poly gates for NMOS and PMOS devices is presented. Due to the midgap work function of the p/sup -/ poly gate, the NMOS native threshold voltage is 0.7 V and, therefore, no additional threshold adjust implantation is required. The NMOS transistor is a surface-channel device with improved field-effect mobility and lower body effect due to the reduction in the channel doping concentration. In addition, the p/sup -/ poly gate is shown to be compatible with p/sup +/ poly-gated surface-channel PMOS devices.<
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