A parallel processor architecture for real-time digital image processing

The authors describe a parallel processor architecture for real-time digital image processing. The processors used are the AT&T WE DSP16A digital signal processors. The system designed consists of multiple DSP16As, and is constructed to perform computations in parallel. The completed hardware system has five DSP16As, and it is expandable to eight. The system uses a customized frame-grabber for image acquisition and display. It is specially tailored to suit the design of the multiple DSP hardware system. The system uses an IBM PC/AT, or compatible as the host. There are two communication paths between the system and the PC. The first uses memory mapped I/O for downloading DSP programs from the PC, and the other for full duplex data and command communication between the DSP and PC during run time.<
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