A novel design for the construction and startup of an eight inch pilot line

An 8-in wafer line with 0.5- mu m CMOS process technology for DRAM and SRAM pilot production is discussed. The pilot line is expected to achieve: (1) speedy construction and startup with overall duration of 16 months; (2) a class-0.1 clean environment at 0.3- mu m particle testing level; (3) the flexibility to advance to 0.2- mu m process technology when needed; (4) the flexibility to enlarge the processing capacity to mass production level (if needed) without interrupting pilot line production. Principles of this design are outlined, difficulties encountered on implementation are discussed, solution approaches employed are illustrated, and preliminary startup results are presented.<
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