The application of temporal logic for flexible scheduling within a high-level synthesis system

An integrated approach for the automatic synthesis of a register transfer architecture from a behavioral description is presented. An internal representation is used based on modeling the temporal relationships between all operations in the specification. A two-phase design approach is presented: design pruning limits the design space through the application of design constraints while design selection produces a timing schedule meeting specific performance characteristics. The rule-based system described has been implemented in PROLOG on a Sun/4. The major advantage of the approach is its generality; unlike many systems, the design process does not operate in a fixed order but is flexible and constraint-oriented.<
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