Resynthesis for testability of redundant combinational circuits

This paper presents an algorithm to generate circuits which are irredundant for stuck-at fault testing but which preserve all the properties of the original design; then any state-of-the-art ATPG procedure can be applied to the modified network. The algorithm makes use of additional control inputs to convert the redundant AND-OR function of the circuit, represented as the sum of all its prime implicants, into the irredundant one.<
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