Incoming inspection of FPGA's

A fault free field programmable array (FPGA) is essential for prototyping design. The authors present a test method that will allow a designer to quickly and efficiently test the FPGA so that he can with confidence know that any errors are design errors and are not due to the presence of manufacturing faults in the FPGA. The fault method is based on a divide and conquer approach for testing regular arrays and allows one to generate test vectors with high fault coverage very efficiently.<
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