Test pattern generation for multiple stuck-at faults

A new method to generate test patterns for multiple stuck-at faults in combinational circuits is presented. All multiple faults of any multiplicity are assumed present in the circuit and one does not have to resort to their explicit enumeration: the target fault is a single component of possibly several multiple faults. The authors try to generate test conditions that propagate the effect of the target fault to primary outputs regardless the effects of other faults which might be present in the circuit. When these conditions are fulfilled, the input vector is a test for the target fault and for all multiple faults containing the target fault as component. The method used a branch-and-bound technique and includes several heuristics to enhance the performance and fault detection. Experiments performed on the ISCAS'85 benchmark circuits show that high fault coverage can be obtained at a reasonable increase in cost.<
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