A performance driven generator for efficient testable conditional-sum-adders

The authors present a performance driven generator for integer adders which is parameterized in n, the operands' bit length, t/sub n/, the delay of the addition, and FM, the (cell based static) fault model. FM may in particular be chosen as the classical stuck-at fault model or the cellular fault model. The output of the generator is an area-minimal n-bit adder of the conditional-sum type with delay >