A flexible VHDL test bench architecture

The author explores test bench designs, based on a flexible architecture, for the testing of systems and subsystems modeling in VHDL. Consideration is given to test bench functionality, and interface designs including the user interface and the interface to the unit under test (UUT). The discussion of the user interface includes test vector input methods as well as techniques for handling test result output. The discussion of the UUT interfaces covers interface design along with techniques for changing this interface as the design of the system progresses (e.g., changing from abstract record passing I/O at early stages of design to physical I/O models as the design matures). A modular design with many reusable clocks forms the basis of the architectures presented.<
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