A methodology for programmable logic migration to ASICs including automatic scan chain insertion and ATPG

Describes a methodology to migrate field programmable logic (FPL) to a gate array or standard cell ASIC with automated schematic translation, functional verification, static timing analysis, and test program generation. The input to the migration flow is the FPL netlist. The translation software replaces existing flip-flops with equivalent scan flip-flops and connects a scan chain. Automatic test pattern generation (ATPG) software then produces high fault coverage test patterns. Timing reports and workstation schematics of the ASIC are available post migration for timing verification and device simulation before manufacturing. This methodology reduces the execution time for FPL migration from man-months to man-days.<
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