A new approach to the problem of PLA partitioning using the theory of the principal lattice of partitions of a submodular function

An area efficient 2 level implementation of combinational logic can be achieved by partitioning the original PLA into several PLAs each of which interacts with the others weakly. A PLA implementing a sum of products logic functions can be modelled through a bipartite graph B/sub G/, which specifies the intersection of rows (minterms) with columns of the AND plane (primary inputs) and the OR plane (primary outputs) respectively. The authors show how to achieve a good PLA partition by using the principal lattice of partitions of the incidence function of B/sub G/.<
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