Behavioral VHDL transistor slope models

Behavioral CMOS transistor models that can accurately predict the timing and logic operation of a custom designed circuit layout are presented. A simple layout extraction program translates the layout netlist to a transistor level VHDL architecture which can be directly simulated, either as a standalone component or as a system module. Simple VHDL constructs and existing delay models were used to develop the transistor models that provide the design engineer with accurate circuit timing and logic information for simulation with higher level models.<
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