Ground bounce and reduction techniques (CMOS VLSI)

VLSI has progressed to reduce the minimum design feature and reduce delay. However, when CMOS circuits rapidly charge or discharge large capacitive loads simultaneously, the corresponding current through the parasitic inductance of the bonding and package lead wiring connecting the chip to one of the power supplies (VDD or VSS) causes a voltage drop to occur. This variation in voltage at the VDD or VSS node with respect to an external ground is called ground bounce. As VLSI improves performance by decreasing delay, ground bounce generation becomes a more serious problem for digital and mixed signal chip designs. The author discusses techniques to reduce ground bounce. One method is to automatically compensate for the normal processing variation's effect on delay and ground bounce. Another is to utilize substrate conduction to reduce the external parasitic inductance.<
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