A testable model for stoppable clock ASICS

A testable model for globally asynchronous ASICs is presented. These circuits operate without a global clock and are useful for pipelined or data-driven architectures. The ASIC can be partitioned into several locally clocked modules and control is distributed throughout these modules. A test methodology is presented which partitions each locally clocked module into synchronous and asynchronous components in test mode. Design for testability techniques are used to further simplify the testing process.<
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