0.3- mu m advanced SAINT FET's having asymmetric n/sup +/-layers for ultra-high-frequency GaAs MMIC's

Improvements in the microwave performance and noise performance of buried p-layer self-aligned gate (BP-SAINT) FETs are discussed. Specifically, a self-aligned gate electrode and an asymmetric n/sup +/-layer structure are investigated. The self-aligned gate electrode reduces parasitic gate capacitances by 0.13 to 0.23 pF/mm compared with a conventional BP-SAINT FET. The asymmetric n/sup +/-layer structure reduces short-channel effects (drain conductance, threshold voltage shift, etc.) and gate-drain capacitance. A 0.3- mu m gate-length FET was realized without an increase of short-channel effects by using an asymmetric n/sup +/-layer structure (advanced SAINT). Improvement of microwave performance is confirmed in this FET structure.<
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