Development of polysilicon TFTs for 16 MB SRAMs and beyond

The authors discuss the development and optimization of polysilicon grain microstructure, gate dielectric ,and light doped drain offset (LDO) for thin-film transistors (TFTs). The nominal TFTs used in this study had a W/L of 0.7/1.2 mu m with a drain offset of 0.3 mu m. Different gate dielectrics (SiO/sub 2/, NO, ONO) with thickness of 10-50 nm were evaluated. The results suggest that an LDO implant is essential for obtaining ON/OFF ratios greater than 10/sup 5/ while reducing the TFT sensitivity to drain-offset misalignment. The ONO dielectric is superior to NO stacks or oxide in terms of oxide leakage and ON/OFF ratios. A 3*10/sup 14/ Si implant after solid-phase crystallization (SPC) improves the slope by reducing the interface trap density. Therefore, significant performance enhancements in leakage (<50 fA) and ON/OFF (>10/sup 6/) can be realized using LDO TFTs with stacked gates and an Si implant following SPC.