A high speed and low power on CMOS/SOI technology

The propagation delay times were improved up to two times in deep-submicron CMOS/SIMOX ring oscillators by reducing the poly-Si gate thickness (t/sub m/). The measured power dissipations with 0.1- to 0.25- mu m gate length are under 1.5 fJ, while theoretical minimum power dissipations can be reduced down to 0.1 fJ for 0.15- mu m gate length at a supply voltage of 1.5 V. SOI technology shows promise for high speed and low power by reducing the gate fringing capacitance which is correlated to t/sub m/.