A 5.9 mu m/sup 2/ super low power SRAM cell using a new phase-shift lithography

A novel 5.89 mu m/sup 2/ memory cell for 16 Mb SRAMs has been developed. The cell is fabricated using a phase-shift photolithography that includes a method for making 0.25 mu m space patterns with the conventional stepper. To reduce cell area, the concept of small cell-ratio is introduced. To overcome the unstable operation of the small-ratio cell, an advanced poly-Si PMOS transistor for load devices is used. To simultaneously obtain stable operation and extremely low standby power dissipation for the memory cell, a self-aligned offset structure for the poly-Si PMOS transistor is proposed and demonstrated. An extremely small leakage current of 2-fA/cell and an on/off-current ratio of 4.6*10/sup 6/ are achieved with this transistor in a memory cell. Memory operation is also demonstrated by an experimental 32 kb SRAM chip.<
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