Low-resistance CVD W plug on Ti silicide for advance CMOS applications

A novel approach is used to form a selective CVD (chemical-vapor-deposited) W plug on a Ti silicide surface by adding a nucleation layer in the contact hole. The technique is called SANIC (self-aligned nucleation layer formation in the contact). The process sequences of SANIC are described and the process latitude of the SANIC technique is examined. The SANIC process has been demonstrated on 1- mu m (drawn) CMOS SRAM and ring oscillators. The CMOS device characteristics and the corresponding gate delays of ring oscillators are shown.<
>