High performance sub-half micron CMOS using rapid thermal processing

A sub-half micron CMOS technology has been developed using rapid thermal processing (RTP) and a simplified process design. The threshold voltages are set high to permit operation above room temperature without excessive leakage. Novel process features include zero-topography well design, RTP CMOS well anneal in an ammonia ambient, RTP gate oxide, RTP source/drain anneal, and BPSG reflow at 750 degrees C in a high-pressure nitrogen ambient. Transistors with 8 nm gate oxide and 0.4 mu m gate lengths provide 65 ps gate delay at 3.3 V. The use of 4*10/sup 17//cm/sup 3/ CMOS well doping without added channel implants results in higher diode capacitance and increases inverter chain delay by approximately 20 ps/stage, but speeds less than 50 ps/stage should be obtained with L=0.3 mu m NMOS and L=0.4 mu m PMOS, both having effective channel lengths of approximately 0.2 mu m.<
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