A split wordline cell for 16 Mb SRAM using polysilicon sidewall contacts

A 16-Mb SRAM (static RAM) cell having three significant features in comparison with conventional cells has been developed. First, a split wordline memory cell layout was adopted. Second, a double-gated PMOS thin film transistor (TFT) load was used. Third, polysilicon sidewall contacts were applied to the cell storage-node to reduce the number of fabrication process steps. The cell size was 2.1 mu m*4.15 mu m and it was fabricated using a conventional i-line stepper; and two phase-shift masks were required for the fabrication process. Memory cell operation was verified using a 64-kb test chip. In order to reduce soft errors, the 'fin' capacitor was applied to the 16-Mb SRAM cell.<
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