The architecture of a processor array for video decompression

Different standards for video compression require a flexible approach for integrating this functionality into multimedia terminals and computers. A programmable processor array (reduced instruction set computer, dataflow, four processor elements) and the corresponding decoding software are presented for this task. Specifically, the simulation results show that the use of fast algorithms combined with careful programming with respect to the statistical behavior of the coded video data leads to high decoding performance. Therefore, despite the fact that it is universally programmable, the processor array has about the same decoding performance/number of devices ratio as dedicated or hybrid architectures. This means that regular, scalable, and universally programmable processor arrays are competitive solutions for MPEG (Motion Picture Experts Group) video decompression and similar kinds of complex data processing algorithms.<
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