Full CMOS video line-locked phase-locked loop system

A CMOS PLL (phase-locked loop) system for generation of a television line-locked clock in the frequency range 25 MHz to 40 MHz is described. The PLL system is designed for use as a generic building block with large-scale CMOS video signal processing integrated circuits. The development of a custom test chip version of the PLL system is reported. A test chip version of the PLL system has been fabricated in 0.8 mu m CMOS technology and tested to verify functionality and examine acquisition and racking behavior. The test chip version of the PLL includes a bidirectional test bus monitor system used to observe 28 signals and input five signals for the purpose of assessing circuit operation details. The open-loop measured noise bandwidth of the RC VCO (voltage-controlled oscillator) is -30 dB at 350 Hz. The short term stability within one second is approximately +or-150 Hz or 20 p.p.m., corresponding to 1.3 ns jitter in one horizontal line period of 63.5 mu s.<
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