Wave-domino logic: timing analysis and applications

Wave-pipelining has been investigated extensively as a design method to increase clock frequencies of digital systems. The authors explore wave-pipelining of domino CMOS circuits because of their compact layouts and shorter delay time. A timing model and constraints are given for deriving the minimal period. Partitioning and restructuring of circuits for wave-pipelining are discussed. A test chip has been designed using a novel form of domino-logic to verify the concept.<
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