Optimization of the number of levels of hierarchy in large-scale hierarchical memory systems

Address decoding is a crucial part of memory operations. It constitutes a major part of the memory access time. One method to reduce the decoding delay for large-scale memory systems is the employment of hierarchical design and the use of a multilevel addressing scheme. The authors present results on optimal levels of hierarchy required, given a memory capacity, to achieve the optimal performance, i.e., the shortest addressing time. The study also compares the highly hierarchical memory structure with the nonhierarchical structures and the widely used divided-word line structure. The results show that a significant amount of speedup in decoding time can be achieved by using the highly hierarchical structure.<>