A study of the use of local interconnect in CMOS leaf cell design

The authors present a leaf-cell layout methodology for harnessing the potential of the local interconnect (LI) layer in digital CMOS circuits. Based on the line-of-diffusion layout style, LI is used for selected connections, typically at the output of logic gates, in order to free up the metal layer in congested areas. The authors present experimental results based on a variety of logic cells which demonstrate the benefit of the LI in terms of cell area, circuit reliability, and routing flexibility.<
>