Optimal realizations of floorplans (VLSI layout)

The problem of selecting a realization for each of the blocks in a VLSI chip's floorplan so that the area of the floorplan is minimized is considered. This is done by repeatedly replacing primitive superblocks by equivalent basic blocks. A linear time algorithm to determine all the needed primitive superblocks is developed. Equivalent basic blocks are found by using L. Stockmeyer's (1983) algorithm if the primitive superblock has a slicing structure and by using branch-and-bound if not. Experimental results are provided.<
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