A bipolar 1.5 Gb/s monolithic phase-locked loop for clock and data extraction

The design of a monolithic phase-locked loop (PLL) used in a gigabit serial data link interface for clock and data extraction is described. Implemented in a triple-metal 25-GHz f/sub t/ bipolar process and consuming 85 mA from a 5 V-supply, the PLL has a wide frequency acquisition range, from 600 MHz to 1.5 GHz, and a recovered clock phase jitter of less than 18.3 ps r.m.s. The PLL requires only one external component (the loop filter capacitor) needs no adjustment, and is suitable for large-scale integration.<
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