A 10 b 300 MHz interpolated-parallel A/D converter

A 10-b A/D converter with a maximum conversion frequency of 300 MHz, which is four times higher than that for reported 10-b A/D converters, is developed. With an interpolated parallel conversion scheme, the severe requirements for V/sub be/ mismatch can be reduced significantly. It is possible to implement an ultrahigh f/sub T/ of a 25 GHz bipolar transistor to the parallel A/D converter with small differential nonlinearity. SNR of 48 dB and total harmonic distortion of 47 dB at the input frequency of 50 MHz can be achieved. By means of folded differential logic circuits, the number of logic gates is reduced to half that of the conventional approach. The chip is composed of 36 K elements and consumes 4.0 W on a 9.0 mm*4.2 mm die.<
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