Variable V/sub cc/ design techniques for battery operated DRAMs

The authors describe a variable V/sub cc/ design technique to extend battery life. Several special circuits for low V/sub cc/, compensated DC generators and wordline drivers are proposed. These are implemented in a 16 M DRAM using 1 polycide, 3 poly, double-metal, and stacked capacitor based 0.4 mu m CMOS technology. The simulated speed of V/sub cc/ variable design is compared with conventional design at 25 degrees C. The slowdown below 2 V is due to threshold voltage and transistor characteristics.<
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