Serial 9 Mb flash EEPROM for solid state disk applications

A 9-Mb flash EEPROM incorporating a serial interface and other features specifically suited for low-cost, high-capacity, low-power solid-state storage systems has been fabricated using a triple polysilicon, single-metal, 0.9- mu m CMOS process. Thin oxide transistors are used for low read and programming voltages, and thick oxide transistors are used for high erase voltage. The memory array utilizes a virtual ground architecture. The cell erases using inter-poly dielectric tunneling and programs using channel hot electron injection. The use of a split channel memory transistor allows the floating gate portion of the cell to be erased to negative thresholds, thus eliminating the over-erase limitation of traditional stacked gate flash cells.<
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