Concurrent error detection in ALUs by recomputing with rotated operands

Analyzes concurrent error detection in arithmetic logic units by recomputing with rotated operands by k bits (RERO-k). Even though RERO-k was suggested as an extension of recomputation with shifted operands by k bits (RESO-k), the RERO implementation for arithmetic operations and its application to carry lookahead adders have not been shown. It is claimed that complex control units should be used to make RERO feasible. This control hardware may add additional faults which are different from the bit-slice faults in the ALU. In this approach, by adding only one spare bit slice in the arithmetic logic unit, RERO is possible for error detection of logical and arithmetic operations in either ripple carry adders and carry lookahead adders without any additional hardware control unit. Proof will be given that RERO-k can detect (k mod n) consecutive errors in logical operations and (k mod (n+1)-1) consecutive errors in arithmetic operations, where n is the length of the original arithmetic logic unit. This demonstrates that RERO preserves all the error detection features of RESO. With less hardware, time redundancy and more flexibility for error detection, the approach makes RERO more appropriate for VLSI designs.<
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