The design of TSC error C/D circuits for SEC/DED codes

A design technique for totally self-checking (TSC) error correcting/detection (C/D) circuits of single error correcting, double error detection (SEC/DED) codes is described. The structure of these circuits achieves concurrent fault detection and location under normal input conditions. A separate internal fault indication is provided. This improves the reliability, maintainability, and availability of the entire fault-tolerant system because faults are repaired before the appearance of input errors. The error C/D circuits are composed of TSC error detectors, error locators, and error correctors. These circuits are two-rail TSC checkers and are designed using an algebraic approach.<
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