2-D discrete cosine transform array processor using non-planar connections

Summary form only given. The authors present a noble implementation of a two-level pipelined array processor that can perform 2-dimensional discrete cosine transform using nonplanar connections among processing elements which are internally bit-serial pipelined. The designs are derived by systematic mapping based on representing an algorithm and its implementation in an n-dimensional grid and relating the two by affine transformation. The implementation is systolic except for one global connection and exploits the full concurrency of the matrix multiplications involved.<
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