Detection of the trapped electron distribution of PMOSFET's after hot-carrier stress

A method of obtaining the spatial distribution of hot-carrier-induced trapped electrons in the gate oxide (N/sub 0t/(x)) of PMOSFETs is introduced with the aid of a two-dimensional simulator. The measured I/sub ds/ versus V/sub ds/ for various V/sub gs/ for low drain bias and I/sub ds/ versus V/sub gs/ have been compared with data obtained from the simulation concerning the obtained spatial distribution of trapped electrons in the gate oxide. There exists a high degree of agreement between the measured current-voltage characteristics after hot-carrier stress and the simulation results concerning the newly obtained spatial distribution of trapped electrons in the gate oxide.<
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