A 180 MHz 0.8 mu m BiCMOS modular memory family of DRAM and multiport SRAM

A family of modular memories with a built-in self-test interface designed using a synchronous self-timed architecture is described. This approach is ideally suited to modular memories embedded within synchronous systems due to its simple boundary specification, excellent speed/power performance, and ease of modelling. The basic port design is self-contained and extensible to any number of ports sharing access to a common-core cell array. The same design has been used to implement modular one-, two-, and four-part SRAMs and a one-port DRAM based on a four-transistor (4-T) cell. The latter provides a 45% core cell density improvement over the one-port SRAM. Nominal access and cycle times of 5.5 ns for 64 kb blocks have been shown for a 0.8 mu m BiCMOS process with no memory process enhancements. System operation at 100 MHz has been demonstrated on a broadband time-switch chip containing 96 kb of two-port SRAM.<
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