Investigation of power distribution strategies for wafer scale integration (WSI)

The problem of power distribution for WSI has been investigated, using SPICE simulations of distribution strategies for a number of wafer sizes under conditions of varying rail dimensions and processor size. Simulations concentrate on strategies used in an earlier, more specific report, involving grid arrangements in double-layer metal. Results support the suggestion that rails must be several hundred square micrometers in cross section to guarantee integrity of the supply. Large processors are seen to be only fractionally more attractive and a decision regarding this would therefore be dominated in practice by yield consideration. A prospective scheme is proposed which involves continuous metal surfaces for power and ground. This promises attractive performance if a practical realization is possible.<
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