A 13000 gate 3 layer metal bipolar gate array

A 13000 gate ECL TTL (emitter-coupled logic/transistor-transistor logic) bipolar logic array featuring 100-ps/gate delay has been developed. A revolutionary design technique was used to significantly reduce the worst-case power consumptions to less than 10 W. A bipolar channelless architecture helps minimize interconnect delay, but still maintains cell utilization to well over 95% without the use of quad-level metal.<
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