A dynamic programming processor for speech recognition

An integrated processor dedicated to the computation of spectral distances and dynamic programming equations for speech recognition systems has been designed. Its 10-MIPS (million-instructions-per-second) power allows real-time recognition of 1000 isolated words and 300 connected words with a fully optimal method. Its flexibility makes it useful for a wide variety of dynamic time-warping algorithms. The chip has been processed in a 2- mu m CMOS technology, includes 127,309 transistors in a 60 mm/sup 2/ area, runs with a 20-MHz clock, and is delivered in a 84-pin PGA (pin-grid array) package. The design includes a fully optimized layout for the data-path and the clock generator, a standard-cell approach for the control logic block and the padring, and a compiled RAM.<
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