Error detection with latency in sequential circuits

An approach is proposed to encoding states of sequential circuits that takes advantage of the concept of error detection with latency, and which is applicable to a much broader class of sequential machines. An encoding methodology is introduced that uses tree codes for online detection of sequencing errors with latency in sequential circuits. This approach has the potential to yield designs with less complexity and greater error coverage than schemes based on block codes. The potential benefits this approach are demonstrated, including increased error coverage with simultaneous reductions in circuit complexity.<
>