Microprocessor testing by instruction sequences derived from random patterns

A novel technique for testing a microprocessor by instruction sequences generated with an LFSR (linear-feedback shift register) is presented. By translating pseudorandom patterns into the mnemonic code an efficient test pattern generator can be constructed in a straightforward way. It is shown that the resulting instruction sequence is equivalent to a functional test but less expensive. Subsequently, fault simulations at gate level show that pseudorandom instruction sequences are a cost-effective alternative to the functional test.<
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