A low-temperature MOS LSI process

A low-temperature process is proposed for the fabrication of MOS LSIs with very small dimensions. Since this process needs no thermal treatment after gate insulation, shallow source/drain junction, ultra-thin gate oxide, and Al gate electrode can be used. The key processes are self-aligned gate pattern reversion using Mo dummy gates and ECR SiO/sub 2/ lift-off, and planarized Al gate electrode filling using resist/Al etch-back. Test devices fabricated to demonstrate the feasibility of this process operate without trouble.<
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