SWEC: a stepwise equivalent conductance timing simulator for CMOS VLSI circuits

Timing simulation has always been considered a crucial step in digital VLSI circuit design. Many researchers have addressed the issues of time efficiency vs. accuracy by using simpler device models and by simplifying the numerical algorithms. StepWise Equivalent Conductance (SWEC) simulation technique is an alternative which approximates the nonlinear transfer characteristic of the transistor with stepwise constant conductances. The authors demonstrate that the time step can be controlled to provide the necessary accuracy in the implicit integration algorithm. A timing simulator has been built based on this principle. The simulator can handle very large CMOS designs. Comparisons have been made with XPsim and SPECS2 using several examples. The results indicate that SWEC exhibits far better efficiency and accuracy.<
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