An analysis of a fault tolerant scheme for processor ensembles

The authors present and analyze a locally redundant (LR) scheme, applicable to a number of interconnection topologies, for designing fault tolerant processor ensembles. A switching structure is presented for reconfiguration, and it is shown that the LR scheme is area-efficient. A model for static analysis (yield) that takes into account processor, switch, and link failures is presented. This dynamic analysis, based on Markov models, includes the determination of operational availability of the fault tolerant system with and without graceful degradation. Closed-form expressions are also obtained for the transition probabilities of the Markov models in terms of the system parameters.<
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