Realistic built-in self-test for static RAMs

The authors present the specification and design of a self-test mechanism for static random-access memories (RAMs). The test algorithm provides excellent fault detection, and its structure is independent of address and data scrambling. The self-test machine generates data backgrounds on chip and is therefore suitable for both bit-oriented and word-oriented SRAMs. It is also suitable for both embedded SRAMs and stand-alone SRAMs, and adapts to boundary-scan environment. Because of the regular and symmetric structure of the test algorithm, the silicon overhead is only 3% for a 16 K synchronous SRAM.<
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