A 32 Mb/s fully-integrated read channel for disk-drive applications

The authors describe a mixed-signal ASIC (application-specific integrated circuit) which integrates the entire disk-drive and read channel by combining bipolar and CMOS circuit techniques and taking advantage of the inherent device properties of each. The chip contains approximately 10000 devices fabricated in a 1.5- mu m 5-V-only BiCMOS process and implements the traditional peak detector architecture supporting zoned-bit recording applications. The 800-mW worst-case power dissipation and pin count of 52 are achieved by reducing the off-chip component requirement to that of bypass and coupling capacitors, the loop filter components for the AGC, and the phase-locked loops. Integration of the continuous-time filter eliminates high-accuracy inductors or capacitors for the lowpass filter/equalizer/differentiator networks. On-chip sampling capacitors for the servo peaks maintain matching between servo channels.<
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