Architectures and algorithms for decoding multi-dimensional lattice codes

The idea of using parallel processors and other hardware architectures for lattice decoding is suggested, and a novel approach is proposed that could provide the basis of a hardware architecture for decoding such codes. Decoders based on this approach could in principle operate at very high rates, limited only by access time of the memories used. Data rates in excess of 1 Gbit/s should be possible. Such decoding rates could bring the advantages of lattice coding to applications, such as microwave telecommunication links, that require very high data rates.<
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