VLSI based design of a battery-operated digital hearing aid

A two-chip design is proposed wherein one chip is responsible for data acquisition and reconstruction while a second chip is dedicated to the digital signal-processing circuitry. A custom digital signal processor, potentially capable of performing over 3*10/sup 6/ multiply accumulate operations per second while consuming less than a fraction of a milliwatt, that is required to implement a four-channel hearing aid, is presented. Power consumption is minimized while maintaining a wide dynamic range through the use of sign/logarithm arithmetic.<
>